As the demand for cheaper, faster, lower power consuming microprocessors increases, so must the device packing density of the integrated circuit (IC). Minimizing transistor dimensions is of paramount importance to the advancement of semiconductor technologies in two respects. First, minimizing transistor dimensions inherently increases the switching speed of the transistor because, for instance, charge carriers such as electrons have a shorter distance to travel between the transistor's source and drain. Because the charge carriers travel a shorter distance they are able to complete the journey in a shorter period of time. Second, minimizing transistor dimensions allows more transistors to be formed in a given area, since the transistors may be spaced closer together. The ability to place more transistors in an IC contained on a semiconductor chip allows more complex and sophisticated functionality to be incorporated into the chip. Therefore, as a result of reducing the size of transistors in an IC, products which use such ICs, such as, for example, home computers, will be able to operate faster and with greater functionality than ever before.
Minimizing transistor dimensions is typically done by minimizing the critical dimension (CD) printable by a given photolithographic technology. The CD for a given photolithographic technology is generally considered the minimum width which that technology can resolve. For example, FIGS. 1a-1f exemplify a typical process sequence used to fabricate a transistor whose dimensions are ultimately dependent on the photolithographic technology employed.
FIG. 1a illustrates a first photolithographic step determining what will ultimately become the minimum size of a transistor being fabricated in a typical semiconductor process. Onto silicon substrate 100 has been grown a silicon dioxide layer 101 (oxide). Polysilicon layer 102 has been deposited onto the oxide layer 101. Polysilicon layer 102 will ultimately become the gate electrode for the resulting transistor while oxide layer 101 will become the gate oxide for the final transistor. Over polysilicon layer 102 has been spun a photoresist layer 103. Photoresist is a material whose chemical composition is sensitive to certain wavelengths of light. Photoresist layer 103 in FIG. 1a is a positive resist. In a positive resist, photochemical changes take place in the photoresist molecules upon exposure to appropriate wavelengths of light. Such photochemical changes results in the exposed regions of the photoresist layer becoming soluble in a particular solvent known as a developer. Therefore, regions of photoresist layer 103 which are exposed to the appropriate light and subsequently immersed in a developer will be dissolved away while regions of photoresist layer 103 which were not exposed to the light will remain insoluble to the developer and remain on the underlying polysilicon layer 102.
105 in FIG. 1a represents a photolithographic mask or reticle. Such a mask contains opaque features 104 affixed to a transparent substrate 113. When mask 105 is placed between an appropriate light source and photoresist layer 103, the opaque region 104 will block the incident light from reaching the respective region of photoresist layer 103. Regions of mask 105 which do not contain opaque features allow incident light to pass through transparent substrate 113 and expose the respective regions of photoresist layer 103. The width 106 of opaque region 104 translates to the critical dimension (CD) 107 of FIG. 1b.
This width 106 will ultimately determine the transistor length of the final transistor. If width 106 is too large, the final transistor will operate slowly and fewer transistors will be able to fit in a given area. However, if width 106 is too narrow, its image may not be accurately resolved onto photoresist layer 103. Resolution of an opaque feature of a photolithographic mask onto a photoresist layer is heavily dependent upon the wavelength of the incident light to which the photoresist is sensitive. Virtually all commercially available photolithographic systems utilize mercury vapor lamps as their illumination source. The most advanced of such photolithographic systems primarily utilize the mercury vapor spectrum having a wavelength range between 390-450 nm. Such systems are known as i-line steppers and are capable of resolving CDs as narrow as 0.4 microns. It should be noted that other technologies are employed in conjunction with the simplistic representation of the photolithographic process depicted in FIG. 1a. For example, in an image reduction system, mirrors and lenses may be utilized to focus a reduced image of the opaque features of a mask onto the surface of a photoresist layer, thereby optically shrinking the image on the mask. In addition, advanced mask technologies such as phase shift masking (PSM) are utilized to better enhance and resolve the masked images onto the photoresist layer. However, it is still a limitation of current transistor fabrication technologies that the CDs of masks ultimately determine the size of the transistors which those masks are used to create.
FIG. 1b shows the silicon substrate 100 of FIG. 1a after photoresist layer 103 has been exposed by the mask 105 and subsequently immersed in a developing solution. The CD 107 of the remaining photoresist feature 103 in FIG. 1b will be approximately proportional to width 106 of mask 105 in FIG. 1a. Using currently available i-line photolithographic systems, CD 107 will be a minimum of 0.4 microns. Photoresist feature 103 of FIG. 1b will now serve to protect the underlying layers from the etch chemistry of a subsequent anisotropic etch.
FIG. 1c shows the silicon substrate 100 depicted in FIG. 1b after an anisotropic polysilicon and oxide etch has been performed. Because the etch is anisotropic, the edges of polysilicon layer 102 and oxide layer 101 will be substantially flush with the edges of photoresist 103. Therefore, the width of the post-etch polysilicon layer under the photoresist 103 will be the same as CD 107 of the photoresist feature 103.
FIG. 1d displays silicon substrate 100 depicted in FIG. 1c after the remainder of photoresist layer 103 has been removed and a tip implant has been performed. As can be seen, the width of polysilicon gate electrode 102 is the same CD 107 that was developed into photoresist layer 103 in FIG. 1b. A dopant material is implanted into the silicon substrate 100 from a direction perpendicular to the substrate. The region in silicon substrate 100 which lies beneath polysilicon gate electrode 102 will be protected from this dopant implant step by polysilicon gate electrode 102. As a result, dopant regions 108a and 108b are formed in silicon substrate 100. Because the polysilicon gate electrode 102 acts as a masking layer to effectively block the dopant implant from forming doped regions within silicon substrate 100 lying beneath polysilicon gate electrode 102, such a technique forms what is known as a self-aligned gate. The structure is said to be self-aligned because the use of the gate electrode as a masking layer effectively aligns the implant regions to its edges.
FIG. 1e shows the substrate of FIG. 1d after an oxide layer 109 has been conformally deposited over the surface of the substrate. As can be seen in FIG. 1e, oxide layer 109 is deposited relatively uniformly along the surface of silicon substrate 100 as well as the surface and sidewalls of polysilicon gate electrode 102. Due to the topographical nature of the substrate in FIG. 1e and the conformally deposited characteristics of oxide layer 109, the thickness of oxide layer 109 (as measured in a direction perpendicular to the surface of the underlying substrate) is greatest in the regions adjacent to the edges of polysilicon gate electrode 102. In other words, oxide layer 109 is thickest where oxide layer 109 is in transition between the surface of silicon substrate 100 and the surface of polysilicon gate electrode 102. This thickness variation in oxide layer 109 may be exploited to create a feature known as a spacer.
FIG. 1f displays the silicon substrate region 100 depicted in FIG. 1e after an anisotropic etch has created spacers from oxide layer 109 and a source/drain implant has been performed. By performing an anisotropic etch of oxide layer 109, the spacers 110a and 110b adjacent to the sides of polysilicon gate electrode 102 are created. Spacers 110a and 110b serve two important functions. First, because these spacers reside along and conform to the edges of polysilicon gate electrode 102 and gate oxide 101, spacers 110a and 110b serve to protect these regions of the transistor from subsequent damage or contamination. Second, spacers 110a and 110b serve to mask the underlying silicon substrate 100 from the subsequent source/drain implant step which creates doped regions 111a and 111b. As described above in conjunction with the tip implant forming tip regions 108a and 108b, polysilicon gate electrode 102 masks the underlying silicon substrate 100 from the source/drain implant which forms regions 111a and 111b. Because spacers 110a and 110b reside above tip regions 108a and 108b, these regions do not receive the higher dose source/drain implant which forms regions 111a and 111b. The regions 108a and 108b are more lightly doped than the regions 111a and 111b in order to improve certain performance characteristics of the transistor such as junction break-down and hot electron injection. The distance 112 between lightly doped tip region 108a on one side of the transistor and lightly doped tip region 108b on the other side of the transistor represents the transistor's approximate length. This is the distance which a charge carrier, such as an electron, must travel in order to induce the current associated with the transistor's "on" state. It is this transistor length 112 which must be reduced in order to improve a transistor's speed, as discussed above.
Note that transistor length 112 is approximately equal to polysilicon gate electrode width 107. This is because it was the polysilicon gate electrode width 107 which initially defined the region into which the tip dopants were implanted in silicon substrate 100. Further note that polysilicon gate electrode width 107 was formed by anisotropically etching around photoresist CD 107. Ultimately, photoresist CD 107 was determined by photolithographic printing of image 104 from mask 105. Therefore, it can be seen that the final transistor length 112, which plays a significant role in determining a transistor's speed and size, is inherently dependent upon the minimum CD which a given photolithographic process is capable of resolving. Because of this perennial link between photolithographic technology and transistor size, much effort and expense has been directed to the continual improvement of photolithographic technologies. However, it is believed that mercury vapor lamps used to generate UV radiation in conventional photolithographic technologies have become the key limiting factor to continued compaction of IC devices.
More advanced and complex photolithographic technologies have been developed to create the next generation of IC devices. Three such technologies include electron beam lithography, x-ray lithography and ion beam lithography. Electron beam lithography involves drawing a circuit pattern directly onto an electron beam sensitive resist material using a narrow stream of electrons. Using electron beam lithography, features as small as 0.1 microns may be printed. However, electron beam systems have been plagued with resolution problems resulting from electron scattering and electron beam resist processing. In addition, electron beam lithographic processes have extremely slow throughput times thereby making such processes nearly unmanufacturable. Also, electron beam lithography systems cost several times what currently available i-line photolithographic systems cost. Ion beam lithography has developed as an alternative to electron beam lithography since ions are less prone to scattering than are electrons. However, no commercially available manufacturable systems have been created.
The theory behind x-ray lithography is that x-rays, having a much smaller wavelength than UV light, can be used to replace UV sources in conventional lithographic processes to create much smaller feature sizes with better resolution. Unfortunately, x-rays are extremely difficult to control because they cannot be bent or focused in the same manner that conventional UV rays may be manipulated. In addition, there are currently no commercially available x-ray systems suitable for production use, nor is there any currently available production process capable of fabricating an effective mask which can selectively block x-rays.
Thus, scientists and engineers continue to expend vast resources in order to advance photolithographic technologies to support continued shrinking of transistor gate lengths in MOS processes. However, what would be most desireable is a manufacturable process whereby transistor gate lengths can be minimized regardless of the photolithographic technology employed.